As a processor unit by which various types of data processing can be flexibly executed, products such as so-called CPU (Central Processing Unit) and MPU (Micro Processor Unit) have come into a practical use at present.
In a data processing system using such a processor unit, an application program in which a plurality of instruction codes are described, and various types of processing data are stored in a memory device. The processor unit sequentially reads the instruction codes and the processing data from the memory device and executes a plurality of types of calculation processing.
The processor unit can realize various types of data processing but has to sequentially execute the plurality of types of calculation processing. Also, because the processor unit has to read one instruction code from the memory device for every processing, it is difficult to execute complicated data processing at high speed.
On the other hand, when data processing to be executed is limited to a single type of processing, the processor unit can avoid the sequential processing by forming an executing section of the data processing in hardware. That is, it is not necessary to sequentially read the plurality of instruction codes from the memory device and to sequentially execute the data processing. However, a logic circuit in hardware can execute complicated data processing at high speed, but can execute only the single type of data processing.
In other words, the data processing system in which application programs can be switched freely can execute various types of data processing but it is difficult to execute the data processing at high speed. On the other hand, the logic circuit in hardware can execute the data processing at high speed but only the single type of data processing can be executed because the application program cannot be switched.
It is a reconfigurable circuit that is provided between these extreme examples. This is a device that can be reconfigured to a predetermined different configuration (logic) according to a necessity. Therefore, the reconfigurable circuit provides a possibility of a computer in which hardware resources are changed to satisfy a need of present computation through appropriate reconfiguration.
In the reconfigurable circuit, many small-scale functional blocks are arranged in a matrix, and an operation of each of many functional blocks and the connection relation of many operation units connected by programmable interconnection resources are switched according to an application program.
The reconfigurable circuit can execute various types of data processing, because the hardware configuration is changed by changing the application program. Also, the reconfigurable circuit can execute the data processing at high speed because the many small-scale functional blocks in hardware execute simple calculation processes in parallel.
The various type of data processing can be realized by the reconfigurable circuit, and various types of programmable interconnection resources are contrived to make it possible to perform an efficient connection between the functional blocks and various circuits. For example, a reconfigurable circuit which has a plurality of interconnection resources of different types in attribute is disclosed in JP 2002-076883A (Patent Literature 1) and JP 2003-076668A (Patent Literature 2). Also, a reconfigurable circuit having a plurality of configurations is disclosed in JP 2000-224025A (Patent Literature 3) and JP 2001-312481A (Patent Literature 4).
In the reconfigurable circuit disclosed in Patent Literature 1, uniform programmable interconnections (interconnection resources) are used in a horizontal direction in which multi-bit data is transferred. Here, high performance multi-bit data path can be efficiently implemented by using programmable interconnections (interconnection resources) suitable for processing in units of an ALU (Arithmetic and Logic Unit) in a same vertical direction as an extension direction of the ALU unit.
In the reconfigurable circuit disclosed in Patent Literature 2, interconnection resources are separately used for m-bit width data path and n-bit width data path (n<m) to efficiently execute data processing of many bits (m-bit) and data processing of small bits (n-bit).
In the reconfigurable circuit, many functional blocks 10 are arranged in a matrix, as shown in FIG. 1. The functional block 10 is configured by arithmetic and logic calculation units exemplified by an ALU unit, a register file, a memory and so on and can set a variety of logical functions in a programmable manner.
Also, the reconfigurable circuit can realize various functions by freely changing the connection relation among the functional blocks 10 by the programmable interconnection resources (buses 20 and 30).
A programmable switch (not shown) to switch the connection relation among the interconnection resources (buses 20 and 30) in the reconfigurable circuit is controlled by a storage element (hereinafter, to be referred to as a configuration data memory) such as a memory and flip-flops (FF). For example, the configuration data memory which stores a plurality of configuration data is disclosed in JP 2008-15772A (Patent Literature 5).
In the above-mentioned Patent Literatures and conventional techniques, programmable switch elements such as an NMOS (N-channel Metal Oxide Semiconductor) transistor, a transmission gate, a tri-state buffer, and a multiplexer are controlled based on the configuration data corresponding to only the elements.